1. Field of the Invention
The present invention relates to a chip structure, and more particularly, to a chip structure that reduces the material usage of bump.
2. Description of Related Art
In the semiconductor industries, the production of integrated circuit (also known as IC, microcircuit, or chip) mainly includes three stages of manufacturing a wafer, forming the integrated circuit on the wafer and packaging the integrated circuit. The integrated circuits are produced in large batches on a single wafer through semiconductor processes, such as photolithography. The wafer is cut into many pieces, and each of these pieces is called as a die, on which a given functional circuit is fabricated. The die is electrically connected with carrier via the pads of the die for forming a chip package structure.
FIG. 1 shows a cross-section view of a conventional chip structure. Referring to FIG. 1, a chip 100 includes a patterned circuit 110, a plurality of pads 120 and a protective layer 130. The pads 120 are disposed on the patterned circuit 110, and the protective layer 130 is disposed on the patterned circuit 110 and a part region of each pad 120. The protective layer 130 includes a plurality of openings for exposing the said part region of each pad 120. Concretely speaking, the protective layer 130 covers the edges of the pads 120, and the central parts of the pads 120 are exposed via the openings.
In the chip structure, a plurality of gold bumps 140 are formed on the pads 120 for electrically connecting the chip 100 with the carrier, such as a packaged board or a flexible printed circuit board. The bumps 140 have the same shape of rectangle pillar, which cover the pads 120 exposed by the openings. As the increase of the gold material cost, the material usage of bump should be reduced to fit in with cost-benefit, but the bumps should maintain the minimum contact area of connecting to the carrier.
In addition, the identification of the pads is very important in the chip, which benefits the chip testing and the package process of bonding the chip to the carrier. For example, as known, a source driver in a display device has a plurality of odd driving channels and a plurality of even driving channels alternatively arranged. When testing a certain driving channel of the source driver, the engineers should count these driving channels for searching the one under test. The time spent on searching unidentifiable pads is wasted and helpless for testing whether the source driver can normally work or performing engineering analysis on the source driver. In package process, the identifiable pads are helpful to align the connection between the chip and the carrier. Therefore, it is worth to make efforts on a new design of the bumps disposed on the pads for reducing the cost and identifying the pads.